Wafer level packaging (WLP) is a type of chip packaging method. After the production of the entire wafer is completed, packaging and testing are directly performed on the wafer. After completing the packaging and testing, the wafer is cut into single chips without wiring or gluing. The wafer level packaging provides small packaging size and maintains desired electrical properties of the wafer after being packaged. The wafer level packaging is easily compatible with wafer fabrication and chip assembly, thus, the process from wafer fabrication to product shipment is simplified, and production cost is reduced.
With the development of packaging technology, a thickness of the packaging structure becomes thinner. A fan-out wafer level packaging (FOWLP) is then developed. In the fan-out wafer level packaging, there is no need to use printed circuit boards (PCBs), but flexible expansion of I/O pads and small packaging area are provided. Therefore, the fan-out wafer level packaging significantly reduces the production cost.
However, the performance of the wafer packaged by the fan-out wafer level packaging is poor and still needs to be improved. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems in the art.